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Conferència "Single-Electron Transistor: next low power consumption device beyond 10mm node?" a càrrec d'Esteve Amat

Quan
13/07/2017 de 11:00 a 13:00
On
Aula 002, edifici C4, campus Barcelona Nord
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logo CNM          logo IONS4SET


13 de juliol de 2017 

Conferència  

“Single-Electron Transistor: next low power consumption device beyond 10 nm node?”  

a càrrec d'Esteve Amat


Curriculum Vitae

 

The research career of Esteve Amat has been always focused on the study on electronics reliability. First, throughout his PhD period in the Electronic Engineering Department of UAB under the supervision of Dra. Rosana Rodriguez, the main research path was study the reliability and characterization of MOSFETs based on high-K materials as a gate dielectric. Moreover, the reliability studies were also focused on to analyse different MOSFET configurations subjected to several stress mechanisms, as Channel Hot-Carrier (CHC) and Bias Temperature Instabilities (BTI).

After his doctorate he won a Juan de la Cierva grant and he joined to the Electronic Engineering Department at UPC, under the supervision of Dr. Antonio Rubio. In UPC, he was involved in an EU project (TRAMS) where the variability impact on the reliability study of different memory cells, as 6T-SRAM and 3T1D-DRAM, was his main research topic. The introduction of FinFET devices on memory cells (SRAM & DRAM) was also a relevant task in UPC. Moreover, Soft Error relevance on the memory cells was one of his main research topics as the devices dimensions and supply voltage is continuously scaled.

Afterwards, he moved for collaboration to CEA-LETI as a post-doc researcher during a year, where he was involved in the study of the FDSOI devices feasibility and reliability at sub-threshold regime in a/synchronous configurations.

Currently, he is collaborating into the National Microelectronic Center (CNM), where he is involved in a European project (Ions4SET) where the main motivation is to manufacture a hybrid SET-FET device able to be operative at room temperature. His main duties will be develop the fabrication process required to manufacture this device.

 

Summary of the talk

 

Billions of tiny computers that can sense and communicate from anywhere are coming online, creating the “Internet of Things” (IoT). As the IoT continues to expand, more and more devices need batteries and plugs. According to Gartner (www.gartner.com), there will be nearly 26 billion devices connected to the IoT by 2020. Therefore, together with improved batteries, advanced computation and communication must be delivered at extremely low-power consumption.

It is well-known that Single-Electron Transistors (SET) are extremely low-energy dissipation devices. CMOS and SETs are complementary: SET is “the champion” of low-power consumption while CMOS advantages like high-speed, driving etc. compensate exactly for SET's intrinsic drawbacks. Unrivalled integration with high performance is expected for hybrid SET-CMOS architectures.

Manufacturability is the roadblock for large-scale use of hybrid SET-CMOS architectures. To assure room temperature (RT) operation, single dots of diameters below 5 nm have to be fabricated, exactly located between source and drain with tunnel distances of a few nm. A reliable CMOS compatible process of co-fabrication of RT-SETs and FETs is not yet available.

 

IONS4SET will pave the way for fabrication of low-energy devices operating at RT using the discovery of a bottom-up self-assembly process. Lithography cannot deliver the feature sizes of
1-3 nm required for RT operation. IONS4SET will provide both, (i) controlled self-assembly of single ~ 2 nm Si dots and (ii) self-alignment of each nano-dot with source and drain at tunneling distances of ~ 2 nm.

The fabrication process of the Si nano-dot involves (i) ion irradiation through a few tens of nm thin Si pillars with an embedded SiO2 layer and (ii) thermal activation of self-assembly. Dot self-assembly works for narrow pillars only, i.e. nano-pillar fabrication is crucial for IONS4SET. Finally, a power saving hybrid SET/CMOS device with a vertical gate-all-around nanowire GAA-SET will be fabricated.

In this context, this talk will be focused on this last project milestone, the manufacturability of the SET device operative at room temperature. We will present the different challenges that appear and the different solutions that are currently under study and evolution.